Reliability Models for SEC/DED Memory With Scrubbing in FPGA-Based Designs

Block RAMs on field-programmable gate arrays (FPGAs) are susceptible to radiation-induced single-event upsets (SEUs) and are usually protected by fault-tolerant techniques such as single error correction/double error correction (SEC/DED) codes and/or scrubbing. Scrubbing can be divided into two categories based on the mechanism that controls the scrubbing interval. With deterministic scrubbing, each memory location is scrubbed (repaired) on a regular basis and the interval is fixed. With probabilistic scrubbing, a word is checked and corrected any time it is accessed (read or written). In this case, the scrubbing interval is exponentially distributed. This paper presents two mean-time-to-failure (MTTF) models for SEC/DED memory with scrubbing, which can be applied to general applications, including FPGA designs. The first one considers only probabilistic scrubbing but takes into account nonuniform scrub rates for different memory locations. The second model combines both deterministic scrubbing and probabilistic scrubbing into a single model. The proposed models provide more accurate MTTF estimates compared with prior models. An FPGA-based DSP application is studied as an example to show how the proposed models can be used for estimating memory reliability and to reveal the impact of probabilistic scrub rates and memory access distributions on memory reliability.