Improvements in polysilicon etch bias and transistor gate control with module level APC methodologies

The targeting of transistor gate length is a primary driver of device performance. The targeting of the physical gate critical dimension (CD) greatly impacts the electrical gate dimension. Traditionally, continual monitoring and manual offsets to compensate for lithographic and etch equipment variability have been used to control gate CDs. This paper discusses how advanced process control techniques were applied to the 0.13-μm polysilicon (poly) patterning process. Both scanner and etch equipment were controlled using a combination of feedforward and feedback loops. As a result, significant engineering labor was saved, and gate CD 3 sigma results improved 12%, correlating to improved device performance and enhanced yield.