Title :
A 65-nm Random and Systematic Yield Ramp Infrastructure Utilizing a Specialized Addressable Array With Integrated Analysis Software
Author :
Karthikeyan, Muthu ; Fox, Stephen ; Cote, William ; Yeric, Greg ; Hall, Michael ; Garcia, John ; Mitchell, Barry ; Wolf, Eric ; Agarwal, Suresh
Author_Institution :
IBM Syst. & Technol. Group, Hopewell Junction, NY
fDate :
5/1/2008 12:00:00 AM
Abstract :
This paper describes a yield learning infrastructure that has been developed and deployed to help rapidly ramp 65-nm random and systematic yield. This infrastructure consists of a 4-Mb addressable-array test circuit with >8000 unique test structures along with customized software and automated analysis routines to distill the large datasets generated. Examples of the successful application of this methodology are provided.
Keywords :
integrated circuit testing; integrated circuit yield; addressable-array test circuit; automated analysis; integrated analysis software; random yield ramp; size 65 nm; storage capacity 4 Mbit; systematic yield ramp; yield learning infrastructure; Application software; Automatic testing; Circuit testing; Helium; Integrated circuit yield; Monitoring; Optical arrays; Probes; Semiconductor device manufacture; Software testing; Process monitoring; semiconductor defects; semiconductor device manufacture; yield optimization;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
DOI :
10.1109/TSM.2008.2000277
