Efficient parallel pipelinable VLSI architecture for finding the maximum binary number

The paper presents an architecture for finding the maximum among a group of k-bit binary numbers suitable for implementation in VLSI. This is done by first presenting a simple algorithm that is easily mapped into VLSI circuits with minimum complexity. A major objective of the design was to determine an efficient parallel pipelinable circuit for finding the maximum when all the bits are available in parallel. Such a unit could be used as an integral part of the Add-Compare-Select (ACS) unit of the Viterbi decoder or any other device that may require the use of a maximum finding circuit in its implementation. Another objective of the paper is to demonstrate that many of the asymptotically optimal algorithms for this problem may be inefficient for a practical VLSI implementation. This is because often these algorithms are written for an entirely different system model. The cost analysis and operational speed of the algorithm are addressed from the implemental point of view as opposed to the more traditional approach of analysing the cost and operational speed based on the number of computations and the number of processors irrespective of the degree of complexity of the units and other relevant routing issues