Clock feedthrough analysis and cancellation in current sample/hold circuits

The clock feedthrough current caused by charge injection in a current sample/hold circuit is investigated. After an overview of the existing cancellation techniques, a novel technique for cancelling both signal-dependent and signal-independent clock feedthrough current is introduced. The narrow channel width effect on the output current of a nonunity current mirror and the clock feedthrough voltage at the gate of the holding transistor are also analysed and simulated using HSPICE. Results show that the proposed circuit not only cancels both signal-dependent and signal-independent clock feedthrough current, but also does not suffer from the narrow channel width effect. The proposed technique is superior to other techniques in terms of clock feedthrough current error, speed and silicon area