Title :
Single event upsets in gallium arsenide dynamic logic
Author :
Fouts, D.J. ; Weatherford, T. ; McMorrow, D. ; Melinger, J.S. ; Campbell, A.B.
Author_Institution :
Naval Postgraduate Sch., Monterey, CA, USA
Abstract :
The advantages and disadvantages of using gallium arsenide (GaAs) dynamic logic in computers and digital systems are briefly discussed, especially with respect to space applications. A short introduction to the topology and operation of GaAs Two-Phase Dynamic FET Logic (TDFL) circuits is presented. Experiments for testing the SEU sensitivity of GaAs TDFL, using a laser to create charge collection events, are described. Results are used to estimate the heavy-ion, soft error rate for TDFL in a spacecraft in geosynchronous orbit, and the dependence of the SEU sensitivity on clock frequency, clock voltage, and clock phase. Analysis of the data includes a comparison between the SEU sensitivities of TDFL and the more common static form of GaAs logic, Directly Coupled FET Logic (DCFL). This is the first reported SEU testing of GaAs dynamic logic.<>
Keywords :
III-V semiconductors; MESFET integrated circuits; field effect logic circuits; gallium arsenide; integrated circuit testing; ion beam effects; logic testing; GaAs; SEU sensitivity; SEU testing; TDFL circuits; charge collection events; clock frequency; clock phase; clock voltage; dynamic logic; geosynchronous orbit; heavy-ion soft error rate; single event upsets; space applications; spacecraft; two-phase dynamic FET Logic; Application software; Circuit topology; Clocks; Digital systems; FETs; Frequency estimation; Gallium arsenide; Logic circuits; Logic testing; Single event upset;
Journal_Title :
Nuclear Science, IEEE Transactions on
