Optimized sensing scheme of DRAMs

Author

Kraus, Rainer ; Hoffmann, Kurt

Author_Institution

Univ. der Bundeswehr Munchen, Neubiberg, West Germany

Volume

24

Issue

4

fYear

1989

fDate

8/1/1989 12:00:00 AM

Firstpage

895

Lastpage

899

Abstract

The half-V_cc sensing scheme of CMOS dynamic RAMs (DRAMs) has been analyzed. It has been found that fluctuations of the cell-plate bias must be taken into account since they can degrade the sense signal. An improvement is possible by connecting the bit lines to the cell plate and its half-V_cc generator during precharge. Optimum performance of the sense amplifier is achieved if the PMOS and NMOS latches are activated simultaneously. The advantages are: (1) the sensitivity is improved due to the elimination of the offset contribution caused by unmatched capacitive loads; (2) the sensing speed is enhanced due to faster sense signal amplification; and (3) the peak current is reduced since the NMOS latch does not lower the voltage level of both bit line and reference bit line

Keywords

CMOS integrated circuits; integrated memory circuits; random-access storage; CMOS dynamic RAMs; DRAMs; NMOS; PMOS; cell-plate bias; offset contribution; peak current; precharge; sense signal; sensing speed; unmatched capacitive loads; Degradation; Fluctuations; Helium; Joining processes; MOS devices; Operational amplifiers; Random access memory; Signal analysis; Signal detection; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.34067

Filename

34067