Title :
A 6.75 ns 16×16 bit multiplier in single-level-metal CMOS technology
Author :
Sharma, Ramautar ; Lopez, Alexander D. ; Michejda, John A. ; Hillenius, Steven J. ; Andrews, John M. ; Studwell, Arnold J.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
fDate :
8/1/1989 12:00:00 AM
Abstract :
A 16×16 bit multiplier integrated circuit fabricated in a CMOS technology having only one level of metallization is described. Microarchitecture for the multiplier has been optimized to balance the delays in different sections of the chip. A typical multiplication time of 6.75 ns at 3.3 V power supply has been measured, and better results are expected from a process optimized for 0.5 μm devices
Keywords :
CMOS integrated circuits; integrated logic circuits; multiplying circuits; 0.5 micron; 3.3 V; 6.75 ns; delays; multiplication time; multiplier; power supply; single-level-metal CMOS technology; CMOS integrated circuits; CMOS technology; Delay; Integrated circuit metallization; Integrated circuit technology; Microarchitecture; Power measurement; Power supplies; Semiconductor device measurement; Time measurement;
Journal_Title :
Solid-State Circuits, IEEE Journal of
