Performance limits of mixed analog/digital circuits with scaled MOSFETs

Author

Sano, Eiichi ; Tsukahara, Tsuneo ; Iwata, Atsushi

Author_Institution

LSI Lab., NTT, Kanagawa, Japan

Volume

23

Issue

4

fYear

1988

Firstpage

942

Lastpage

949

Abstract

Constant electric field (CE), quasi-constant voltage (QCV), and constant voltage (CV) scaling laws are used as guides to MOSFET miniaturization. It is found that: 1) the QCV scaling law gives the best performance of the three scaling laws; 2) improvements in unity-gain bandwidth with scaling are less than predicted by the first-order theory due to mobility degradation; 3) gate length can be scaled down to 0.25 mu m while maintaining 10-bit accuracy for analog circuits (threshold variation limit); and 4) when gate lengths deviate from designed values, noise immunity for digital circuits is degraded mainly due to degradation in the saturation characteristics (drain-induced barrier lowering).<>

Keywords

VLSI; digital integrated circuits; electron device noise; field effect integrated circuits; insulated gate field effect transistors; semiconductor device models; 0.25 micron; 10-bit accuracy; MOSFET miniaturization; VLSI; constant electric field type; constant voltage; drain-induced barrier lowering; first-order theory; gate length; mixed analog/digital circuits; mobility degradation; noise immunity; quasi-constant voltage; saturation characteristics degradation; scaled MOSFETs; scaling laws; threshold variation limit; unity-gain bandwidth; Analog circuits; Capacitance-voltage characteristics; Circuit noise; Circuit optimization; Degradation; Digital circuits; Large scale integration; MOSFETs; Subthreshold current; Threshold voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.345

Filename

345