32-channel digital 6-bit TDC with 2.5 ns least count

The authors have built, and used to take physics data, a 5000-channel common start TDC system in which each channel has a 6-bit range with a nominal least count of 2.5 ns. The rms error on the time, as measured with a commercial 100 ps TDC, is less than 0.8 ns for all channels. They use ECL 10 K technology for all but the gray code clock bits, which they generate and fan out with 100 K ECL. The 32-channel boards are part of the custom readout system which includes an extra buffer just after each channel´s digitizing circuitry. Immediately after digitization, the data are shifted to these buffers, so that the front end can be re-enabled for the next event while readout from the buffers through the crate controllers proceeds independently at 100 ns per hit channel. The reliability is excellent, with negligible failures of the 30000-chip system during four months of running of BNL AGS Experiment 791 in 1987 and 1988