Title :
Low-power CMOS threshold-logic gate
Author :
Avedillo, M.J. ; Quintana, J.M. ; Rueda, A. ; Jiménez, E.
Author_Institution :
Dept. de Diseno Analogico, Seville Univ., Spain
fDate :
12/7/1995 12:00:00 AM
Abstract :
A new implementation of a threshold gate based on a latch-type comparator that does not consume static power is presented. Simulation results indicate high operation speed and low power consumption, which make it very attractive when used as a basic building block in digital design
Keywords :
CMOS logic circuits; logic gates; threshold logic; CMOS logic gate; high operation speed; latch-type comparator; low power consumption; threshold-logic gate;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19951471
