Title :
FPGA implementation of synchronous section-carry based carry look-ahead adders
Author :
Preethi, K. ; Balasubramanian, P.
Author_Institution :
Department of PG Studies in Engineering S.A. Engineering College (Affiliated to Anna University) Chennai 600 077, Tamil Nadu, India
Abstract :
It is common knowledge that carry look-ahead adders constitute a high-speed method of performing binary addition in logarithmic time. As an improvement, in this paper, FPGA based realization of high-speed carry look-ahead adders based on the concept of section-carry is discussed. Three kinds of carry look-ahead adder architectures viz. Type 1, Type 2, Mixed are presented. In comparison with conventional carry look-ahead adders of sizes 16, 32 and 64-bits, the proposed section-carry based carry look-ahead adders report improvements in speed of 14.9%, 12.1% and 13% for Type 1, Type 2 and Mixed topologies respectively, for simulations targeting a 90nm FPGA device.
Keywords :
Adders; CMOS integrated circuits; Computer architecture; Delays; Educational institutions; Field programmable gate arrays;
Conference_Titel :
Devices, Circuits and Systems (ICDCS), 2014 2nd International Conference on
Conference_Location :
Combiatore, India
DOI :
10.1109/ICDCSyst.2014.6926150
