• DocumentCode
    12281
  • Title

    Design Techniques for Xilinx Virtex FPGA Configuration Memory Scrubbers

  • Author

    Herrera-Alzu, I. ; Lopez-Vallejo, Marisa

  • Author_Institution
    Dept. of Electron. Eng., Univ. Politec. de Madrid, Madrid, Spain
  • Volume
    60
  • Issue
    1
  • fYear
    2013
  • fDate
    Feb. 2013
  • Firstpage
    376
  • Lastpage
    385
  • Abstract
    SRAM-based FPGAs are in-field reconfigurable an unlimited number of times. This characteristic, together with their high performance and high logic density, proves to be very convenient for a number of ground and space level applications. One drawback of this technology is that it is susceptible to ionizing radiation, and this sensitivity increases with technology scaling. This is a first order concern for applications in harsh radiation environments, and starts to be a concern for high reliability ground applications. Several techniques exist for coping with radiation effects at user application. In order to be effective they need to be complemented with configuration memory scrubbing, which allows error mitigation and prevents failures due to error accumulation. Depending on the radiation environment and on the system dependability requirements, the configuration scrubber design can become more or less complex. This paper classifies and presents current and novel design methodologies and architectures for SRAM-based FPGAs, and in particular for Xilinx Virtex-4QV/5QV, configuration memory scrubbers.
  • Keywords
    SRAM chips; field programmable gate arrays; integrated circuit reliability; SRAM-based FPGA; Xilinx Virtex FPGA; Xilinx Virtex-4QV/5QV; configuration memory scrubbers; error accumulation; error mitigation; harsh radiation environments; in-field reconfigurable; ionizing radiation; logic density; reliability ground; technology scaling; Error correction codes; Field programmable gate arrays; Radiation effects; Reliability; Routing; Single event upset; Tunneling magnetoresistance; Field Programmable Gate Array (FPGA); Xilinx; reconfiguration; scrubbing; single event upset;
  • fLanguage
    English
  • Journal_Title
    Nuclear Science, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0018-9499
  • Type

    jour

  • DOI
    10.1109/TNS.2012.2231881
  • Filename
    6412749