DocumentCode :
1228242
Title :
Min-cost flow-based algorithm for simultaneous pin assignment and routing
Author :
Xiang, Hua ; Tang, Xiaoping ; Wong, Martin D F
Author_Institution :
Comput. Sci. Dept., Univ. of Illinois, Urbana-Champaign, IL, USA
Volume :
22
Issue :
7
fYear :
2003
fDate :
7/1/2003 12:00:00 AM
Firstpage :
870
Lastpage :
878
Abstract :
Macroblock pin assignment and routing are important tasks in physical design. Existing algorithms for these problems can be classified into two categories: 1) a two-step approach where pin assignment is followed by routing and 2) a net-by-net approach where pin assignment and routing for a single net are performed simultaneously. However, none of the existing algorithms is "exact" in the sense that they may fail to route all of the nets even though a feasible solution exists. This remains to be true even if only two-pin nets with fixed pins between two blocks are concerned. In this paper, we consider the problem of two-pin net connections from one macroblock to all of the other blocks, and present the first polynomial-time exact algorithm for simultaneous pin assignment and routing for all of the two-pin nets between one block (source block) and all of the other blocks. In addition to finding a feasible solution whenever one exists, it guarantees to find a pin-assignment/routing solution with minimum cost α·W+β·V, where W is the total wire length and V is the total number of vias. Our algorithm has various applications. 1) It is suitable in engineering change order (ECO) situations where the existing solution is modified incrementally. 2) Given any pin assignment and routing solution obtained by any existing method, our algorithm can be used to increase the number of routed nets and reduce the routing cost. Furthermore, it provides an efficient algorithm for the pin assignment and routing problem of all of the blocks. The method is applicable to both global and detailed routing with arbitrary routing obstacles on multiple layers. Experimental results demonstrate its efficiency and effectiveness.
Keywords :
VLSI; circuit layout CAD; circuit optimisation; flow graphs; integrated circuit layout; network routing; PAR-by-Flow algorithm; VLSI design; arbitrary routing obstacles; engineering change order situations; global routing; macroblock pin assignment; min-cost flow-based algorithm; minimum cost solution; physical design; polynomial-time exact algorithm; routing; source block; three-dimensional multilayer routing grid graph; two-pin net connections; Computer science; Costs; Large-scale systems; Pins; Polynomials; Routing; Runtime; Silicon; Wire;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2003.814258
Filename :
1208446
Link To Document :
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