DocumentCode :
123163
Title :
PETS: Power and energy estimation tool at system-level
Author :
Rethinagiri, Santhosh-Kumar ; Palomar, Oscar ; Unsal, Ozan ; Cristal, Adrian ; Ben-Atitallah, Rabie ; Niar, Smail
Author_Institution :
Barcelona Supercomput. Center, Barcelona, Spain
fYear :
2014
fDate :
3-5 March 2014
Firstpage :
535
Lastpage :
542
Abstract :
In this paper, we introduce PETS, a simulation based tool to estimate, analyse and optimize power/energy consumption of an application running on complex state-of-the-art heterogeneous embedded processor based platforms. This tool is integrated with power and energy models in order to support comprehensive design space exploration for low power multi-core and heterogeneous multiprocessor platforms such as OMAP, CARMA, Zynq 7000 and Virtex II Pro. Moreover, PETS is equipped with power optimization techniques such as dynamic slack reduction and work load balancing. The development of PETS involves two steps. First step: power model generation. For the power model development, functional-level parameters are used to set up generic power models for the different components of the system. So far, seven power models have been developed for different architectures, starting from the simple low power architecture ARM9 to the very complex DSP TI C64x. Second step: a simulation based virtual platform framework is developed using SystemC IP´s and JIT/ISS compilers to accurately grab the activities to estimate power. The accuracy of our proposed tool is evaluated by using a variety of industrial benchmarks. Estimated power and energy values are compared to real board measurements. The power estimation results are less than 4% of error for single core processor, 4.6% for dual-core processor, 5% for quad-core, 6.8% multi-processor based system and effective optimisation of power/energy for the applications.
Keywords :
embedded systems; low-power electronics; multiprocessing systems; CARMA; DSP TI C64x; JIT-ISS compilers; OMAP; PETS; SystemC IP; Virtex II Pro; Zynq 7000; comprehensive design space exploration; dual-core processor; dynamic slack reduction; energy estimation tool; functional-level parameters; generic power models; heterogeneous embedded processor based platforms; heterogeneous multiprocessor platforms; industrial benchmarks; low power architecture ARM9; multicore platforms; power estimation tool; power optimization techniques; quad-core; real board measurements; single core processor; virtual platform framework; work load balancing; Estimation; Hardware; Load modeling; Optimization; Positron emission tomography; Process control; Solid modeling;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Quality Electronic Design (ISQED), 2014 15th International Symposium on
Conference_Location :
Santa Clara, CA
Print_ISBN :
978-1-4799-3945-9
Type :
conf
DOI :
10.1109/ISQED.2014.6783373
Filename :
6783373
Link To Document :
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