High-gain wideband error amplifier topology for DC-DC buck converter switching at 20 MHz

A wideband error amplifier topology with increased DC-gain and reduced quiescent current consumption is presented. The reduction in quiescent current consumption is achieved by lowering the output stage current, which helps to increase the output impedance and hence the overall DC-gain of the amplifier. Simulation results show that the proposed topology has 60 dB DC gain and 540 MHz unity gain bandwidth with 450 muA quiescent current consumption. The experimental result of the loop-gain of a high-frequency (20 MHz) DC-DC buck converter that utilises the proposed topology also confirms the simulation results.