• DocumentCode
    1235898
  • Title

    Memory-efficient and high-throughput decoding of quasi-cyclic LDPC codes

  • Author

    Dai, Yongmei ; Yan, Zhiyuan ; Chen, Ning

  • Author_Institution
    Dept. of Electr. & Comput. Eng., Lehigh Univ., Bethlehem, PA
  • Volume
    57
  • Issue
    4
  • fYear
    2009
  • fDate
    4/1/2009 12:00:00 AM
  • Firstpage
    879
  • Lastpage
    883
  • Abstract
    We propose turbo-sum-product (TSP) and shuffled-sum-product (SSP) decoding algorithms for quasi-cyclic low-density parity-check codes, which not only achieve faster convergence and better error performance than the sum-product algorithm, but also require less memory in partly parallel decoder architectures. Compared with the turbo decoding algorithm, our TSP algorithm saves the same amount of memory and may achieve a higher decoding throughput. The convergence behaviors of our TSP and SSP algorithms are also compared with those of the SP, turbo, and shuffled algorithms by their extrinsic information transfer (EXIT) charts.
  • Keywords
    cyclic codes; decoding; parity check codes; product codes; turbo codes; SSP algorithm; TSP algorithm; extrinsic information transfer chart; low-density parity-check codes; memory-efficient architecture; parallel decoder architecture; quasi-cyclic LDPC codes; shuffled-sum-product algorithm; turbo-sum-product algorithm; Convergence; Hardware; Iterative algorithms; Iterative decoding; Mercury (metals); Message passing; Parity check codes; Scheduling algorithm; Sum product algorithm; Throughput; LDPC, quasi-cyclic, turbo decoding, shuffled decoding, sum-product decoding, EXIT charts;
  • fLanguage
    English
  • Journal_Title
    Communications, IEEE Transactions on
  • Publisher
    ieee
  • ISSN
    0090-6778
  • Type

    jour

  • DOI
    10.1109/TCOMM.2009.04.060349
  • Filename
    4814348