Demonstration of decimation filter and high-speed testing of a component of the filter

Author

Sekiya, A. ; Tanaka, M. ; Akahori, A. ; Fujimaki, A. ; Hayakawa, H.

Author_Institution

Dept. of Inf. Electron., Nagoya Univ., Japan

Volume

13

Issue

2

fYear

2003

fDate

6/1/2003 12:00:00 AM

Firstpage

579

Lastpage

582

Abstract

We study decimation filters based on the single-flux-quantum circuit in order to realize over-sampled AD converter. We designed the decimation digital filters using CONNECT cells, a well-developed cell library. We designed a T1 cell, because the T1 cell is the key for the counting-type decimation filter. We confirmed correct operation up to 43 GHz by using an on chip test system. Using the T1 cell, we designed second-order counting-type decimation sinc filters with decimation factors N=2 and N=4. The circuit scale was as high as 2758 junctions. We also confirmed the correct operation of these filters.

Keywords

analogue-digital conversion; cellular arrays; integrated circuit testing; superconducting integrated circuits; 43 GHz; CONNECT cells; cell library; decimation filter; high-speed testing; on chip test system; over-sampled AD converter; sine filters; single-flux-quantum circuit; software-defined radio; Circuit simulation; Circuit testing; Digital filters; Hardware design languages; Josephson junctions; Receivers; Software libraries; System testing; System-on-a-chip; Timing;

fLanguage

English

Journal_Title

Applied Superconductivity, IEEE Transactions on

Publisher

ieee

ISSN

1051-8223

Type

jour

DOI

10.1109/TASC.2003.813951

Filename

1211669