• DocumentCode
    1237363
  • Title

    Acquisition-time estimation for over 10 Gbit/s clock and data recovery ICs

  • Author

    Kishine, K. ; Onodera, H.

  • Author_Institution
    NTT Microsyst. Integration Labs., Atsugi, Japan
  • Volume
    41
  • Issue
    23
  • fYear
    2005
  • Firstpage
    1273
  • Lastpage
    1275
  • Abstract
    A method to estimate the acquisition time for the clock and data recovery (CDR) IC using the linear phase-locked loop (PLL) technique is proposed. Estimations using the method follow the measured acquisition time for the PLL with any loop parameters, which makes it possible to design the CDR IC for various targets.
  • Keywords
    bipolar digital integrated circuits; clocks; phase locked loops; synchronisation; timing circuits; 10 Gbit/s; acquisition-time estimation; clock and data recovery integrated circuit; linear phase locked loop;
  • fLanguage
    English
  • Journal_Title
    Electronics Letters
  • Publisher
    iet
  • ISSN
    0013-5194
  • Type

    jour

  • DOI
    10.1049/el:20052776
  • Filename
    1541767
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1237363