Test generation with dynamic probe points in high observability testing environment

Author

Choy, Oliver Chiu-Sing ; Lap-Kong Chan ; Chan, Ray ; Chan, Cheong F.

Author_Institution

Dept. of Electron. Eng., Chinese Univ. of Hong Kong, Shatin, Hong Kong

Volume

45

Issue

1

fYear

1996

fDate

1/1/1996 12:00:00 AM

Firstpage

88

Lastpage

96

Abstract

High observability testing environment allows internal circuit nodes to be used as test points. However, such flexibility requires the development of new ATPG algorithm. Previous reported algorithm does not guarantee full fault-coverage and assumes all internal circuit nodes are test points. The new algorithm described in this paper will generate a full fault-coverage test set for a fanout free combinational circuit. The main characteristic of the algorithm is that it generates test vectors as well as probe points. As a result, the probe points are different for each test vector, and the number of probe points is the minimum for test set generated. Results obtained show that an average of 30% test vector reduction is achieved compared with the conventional test method which uses only output pins as test points

Keywords

combinational circuits; critical path analysis; integrated circuit testing; integrated logic circuits; logic testing; ATPG algorithm; E-beam testing; automatic test pattern generation; combinational circuit; critical path tracing; dynamic probe points; fanout free combinational circuit; high observability testing; test vector; wafer stage testing; Circuit faults; Circuit testing; Electron beams; Electronic equipment testing; Fault detection; Integrated circuit interconnections; Logic testing; Observability; Probes; Sequential analysis;

fLanguage

English

Journal_Title

Computers, IEEE Transactions on

Publisher

ieee

ISSN

0018-9340

Type

jour

DOI

10.1109/12.481489

Filename

481489