• DocumentCode
    124011
  • Title

    RAM-based hardware accelerator for network data anonymization

  • Author

    Yamaguchi, Fabian ; Matsui, K. ; Nishi, Hidetaka

  • Author_Institution
    Grad. Sch. of Sci. & Technol., Keio Univ., Yokohama, Japan
  • fYear
    2014
  • fDate
    2-4 Sept. 2014
  • Firstpage
    1
  • Lastpage
    4
  • Abstract
    Many network services including intrusion detection and recommendation provide their services by analyzing information acquired from network transactions. A careful analysis of these data can reveal valuable information when deep packet inspection is performed. Since these packet analyses generate sensitive information from enormous volumes of transmitted data, the requirement for data anonymization has been discussed. There have been many studies of anonymization techniques and their implementation in software applications. However, limited research has been undertaken regarding hardware-based anonymizers. This paper proposes and evaluates a RAM-based anonymization architecture that maintains both high throughput and a low information-loss ratio.
  • Keywords
    memory architecture; random-access storage; RAM-based anonymization architecture; RAM-based hardware accelerator; anonymization techniques; deep packet inspection; hardware-based anonymizers; information-loss ratio; intrusion detection; network data anonymization; network services; network transactions; packet analyses; recommendation; sensitive information; Field programmable gate arrays; Hardware; Random access memory; Software; Table lookup; Throughput; Anonymization; Deep Packet Inspection; FPGA; k-anonymity; l-diversity;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Field Programmable Logic and Applications (FPL), 2014 24th International Conference on
  • Conference_Location
    Munich
  • Type

    conf

  • DOI
    10.1109/FPL.2014.6927400
  • Filename
    6927400