DocumentCode
1241585
Title
New operation mode for stacked-gate flash memory cell
Author
Gotou, Hiroshi
Author_Institution
Dev. Dept., NKK Corp., Kanagawa, Japan
Volume
16
Issue
3
fYear
1995
fDate
3/1/1995 12:00:00 AM
Firstpage
121
Lastpage
123
Abstract
A new operational mode is proposed that lowers the threshold voltage of a stacked-gate flash memory cell. The mode features the set-up of the word-line voltage and bit-line voltage. An AC signal is applied to a word-line while a bit-line is kept floating after it is charged. The signal is applied to lower the threshold voltage of the cell and to test it. A SPICE simulation of this operation has revealed that the converged voltage of floating gate has negligible dependency on the initial voltage and the tunnel oxide thickness and that the cell threshold voltage is controllable through the world-line voltage. This operation mode is easily applicable to a conventional flash memory. Furthermore, it may allow the use of flash cells in analog applications or in multi-level memory cells.<>
Keywords
EPROM; SPICE; circuit analysis computing; integrated memory circuits; SPICE simulation; bit-line voltage; flash memory cell; operation mode; stacked-gate memory cell; threshold voltage; word-line voltage; Capacitors; Circuits; Flash memory; Flash memory cells; Nonvolatile memory; SPICE; Testing; Thickness control; Threshold voltage; Voltage control;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/55.363244
Filename
363244
Link To Document