Two quadrant analogue squarer circuit based on MOS square-law characteristic

A novel analogue CMOS circuit is presented which performs the arithmetical squaring of a voltage, using the square-law characteristic of the MOS transistor in saturation. The core circuit is constructed from four identical building blocks, which are connected so as to eliminate all unwanted offset terms. Simulation results from HSPICE are presented where the circuit is used for doubling the frequency of a sinusoidal input.