A path-oriented algorithm for the cell selection problem

An algorithm for the cell selection problem is presented. Given a network G of logic gates, the problem is to select a library cell for each gate such that the longest delay through G is at most T_max and the total area of selected cells is minimum. We first prove the strong NP-completeness of the problem if the circuit is a general acyclic graph. The proof implies that there exists no pseudopolynomial time algorithm unless P=NP. We next propose a path-oriented, heuristic algorithm that iteratively chooses paths of gates with delay larger than T_max, and then selects cells for the paths. The set of paths chosen induces a series-parallel subgraph. We also present a cloning method which further improves a solution obtained by the path-oriented algorithm. In the proposed cloning method, nodes are duplicated into clones such that the resulting graph becomes a series-parallel graph. Our cloning method is more efficient in terms of time and space than the tree cloning of Chan (1990). The results of our algorithm are compared to those Lin et al. (1990). The algorithm provides significantly better solutions to all the circuits than the previous work