High reliability electron-ejection method for high density flash memories

Author

Kawahara, Takayuki ; Miyamoto, Naoki ; Saeki, Syun-ichi ; Jyouno, Yusuke ; Kato, Masataka ; Kimura, Katsutaka

Author_Institution

Central Res. Lab., Hitachi Ltd., Kokubunji, Japan

Volume

30

Issue

12

fYear

1995

fDate

12/1/1995 12:00:00 AM

Firstpage

1554

Lastpage

1562

Abstract

To minimize the electrical stress for electron-ejection of each flash memory cell, the variable word-line voltage (VVP) method and the variable pulse width (VVWP) method are proposed. Both methods make it possible to achieve high reliability while maintaining the total operating time of the conventional method, and both provide a sufficient disturb margin. Simulation results show that both methods reduce the maximum Fowler-Nordheim tunnel current density by 1.4 orders of magnitude compared to that of the conventional method, and the VVWP method increases the number of verifications by much less than the VVP method. This is expected to triple the charge-to-breakdown (Q_bd) by decreasing the trap generation. A Q_bd higher than the injection charge as obtained, as needed for high density flash memories

Keywords

EPROM; current density; integrated circuit reliability; integrated memory circuits; tunnelling; Fowler-Nordheim tunnel current density; charge-to-breakdown; disturb margin; electrical stress minimisation; electron-ejection method; high density flash memories; high reliability; trap generation reduction; variable pulse width; variable word-line voltage method; Current density; Design for quality; Dielectric films; Flash memory; Flash memory cells; Maintenance; Solid state circuits; Space vector pulse width modulation; Stress; Voltage;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.482206

Filename

482206