A 10-Bit 500-MS/s 55-mW CMOS ADC

Author

Verma, Ashutosh ; Razavi, Behzad

Author_Institution

Electr. Eng. Dept., Univ. of California, Los Angeles, CA, USA

Volume

44

Issue

11

fYear

2009

Firstpage

3039

Lastpage

3050

Abstract

A pipelined ADC incorporates a digital foreground calibration technique that corrects errors due to capacitor mismatch, gain error, and op amp nonlinearity. Employing a highspeed, low-power op amp topology and an accurate on-chip resistor ladder and designed in 90-nm CMOS technology, the ADC achieves a DNL of 0.4 LSB and an INL of 1LSB. The prototype digitizes a 233-MHz input with 53-dB SNDR while consuming 55 mW from a 1.2-V supply.

Keywords

CMOS integrated circuits; analogue-digital conversion; calibration; low-power electronics; operational amplifiers; CMOS technology; analogue-digital converters; capacitor mismatch; digital foreground calibration; frequency 233 MHz; gain error; on-chip resistor ladder; operational amplifier nonlinearity; power 55 mW; voltage 1.2 V; word length 10 bit; Analog-digital conversion; CMOS technology; Calibration; Capacitors; Error correction; Operational amplifiers; Prototypes; Resistors; Signal resolution; Topology; Calibration by inverse function; foreground digital calibration; low gain op amp; nonlinearity correction; pipelined analog-to-digital converter; resistor-ladder DAC;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/JSSC.2009.2031044

Filename

5308600