Title :
SHORTFINDER: a graphical CAD tool for locating net-to-net shorts in VLSI chip layouts
Author :
Gannett, Joel W.
Author_Institution :
VLSI Design Methodology Res. Group, Morristown, NJ, USA
fDate :
6/1/1990 12:00:00 AM
Abstract :
Locating the geometrical features causing shorts is often the most vexing problem faced during the layout verification process. A description is given of an interactive CAD tool called Shortfinder that enables the user to find VLSI layout errors resulting in electrical shorts between complex nets quickly and with minimal effort. This is accomplished by displaying a cycle-free shortest electrical path between two points indicated by the user on a graphical display of the layout. Shortfinder was implemented as a modular enhancement to an existing layout viewing program; its data structures and algorithms are described
Keywords :
VLSI; circuit layout CAD; fault location; interactive systems; SHORTFINDER; VLSI chip layouts; algorithms; data structures; electrical shorts; geometrical features; graphical CAD tool; net-to-net shorts; Clocks; Computer bugs; Data structures; Design automation; Design methodology; Displays; Layout; Power generation; Power supplies; Very large scale integration;
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
