DocumentCode :
1252970
Title :
SMT layout overhead and scalability
Author :
Burns, James ; Gaudiot, Jean-Luc
Author_Institution :
Intel Corp., Santa Clara, CA, USA
Volume :
13
Issue :
2
fYear :
2002
fDate :
2/1/2002 12:00:00 AM
Firstpage :
142
Lastpage :
155
Abstract :
Simultaneous Multi-Threading (SMT) is a hardware technique that increases processor throughput by issuing instructions simultaneously from multiple threads. However, while SMT can be added to an existing microarchitecture with relatively low overhead, this additional chip area could be used for other resources such as more functional units, larger caches, or better branch predictors. How large is the SMT overhead and at what point does SMT no longer pay off for maximum throughput compared to adding other architecture features? This paper evaluates the silicon overhead of SMT by performing a transistor/interconnect-level analysis of the layout. We discuss microarchitecture issues that impact SMT implementations and show how the Instruction Set Architecture (ISA) and microarchitecture can have a large effect on the SMT overhead and performance. Results show that SMT yields large performance gains with small to moderate area overhead
Keywords :
multi-threading; parallel architectures; SMT; layout area estimation; microarchitecture; processor architecture; processor throughput; simultaneous multi-threading; Hardware; Instruction sets; Microarchitecture; Performance analysis; Performance evaluation; Scalability; Silicon; Surface-mount technology; Throughput; Yarn;
fLanguage :
English
Journal_Title :
Parallel and Distributed Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1045-9219
Type :
jour
DOI :
10.1109/71.983942
Filename :
983942
Link To Document :
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