DocumentCode
1254663
Title
An analysis of system level power management algorithms and their effects on latency
Author
Ramanathan, Dinesh ; Irani, Sandra ; Gupta, Rajesh K.
Author_Institution
Dept. of Inf. & Comput. Sci., California Univ., Irvine, CA, USA
Volume
21
Issue
3
fYear
2002
fDate
3/1/2002 12:00:00 AM
Firstpage
291
Lastpage
305
Abstract
The problem of power management for an embedded system is to reduce system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when requests have to be serviced. Algorithms for this problem are online in nature; the algorithm must operate only with access to data that it has seen so far and without access to the complete data set or its characteristics. We present online algorithms to manage power for embedded systems and discuss their effects on system latency. We introduce competitive analysis as a formal framework for the evaluation of various power management algorithms. Competitive analysis does not depend on the distribution of interarrival times of requests. We present a nonadaptive online algorithm, analyze its behavior, and show that it is optimal. We also present a lower bound on the competitiveness of any adaptive algorithm. We show that no adaptive online algorithm can dissipate less than about 1.6 times the power dissipated by the optimal offline algorithm in the worst case. We also show that in order for any online algorithm to achieve this lower bound, it may have to maintain a complete history of the interarrival. times of the requests in the input sequence. Since this is not practical, we present a simple algorithm that uses only the last interarrival time to predict the arrival of the next request
Keywords
VLSI; circuit CAD; circuit optimisation; integrated circuit design; logic CAD; low-power electronics; IC design; VLSI; competitiveness; embedded system; formal framework; input sequence; interarrival times; lower bound; nonadaptive online algorithm; optimal offline algorithm; power dissipation; system latency; system level power management algorithms; worst case performance; Adaptive algorithm; Algorithm design and analysis; Delay; Embedded system; Energy management; Portable computers; Power dissipation; Power system management; Turning; Very large scale integration;
fLanguage
English
Journal_Title
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher
ieee
ISSN
0278-0070
Type
jour
DOI
10.1109/43.986423
Filename
986423
Link To Document