Title :
A 14-ns 1-Mbit CMOS SRAM with variable bit organization
Author :
Kohno, Yoshio ; Wada, Tomohisa ; Anami, Kenji ; Kawai, Yuji ; Yuzuriha, Kojiro ; Matsukawa, Takayuki ; Kayano, Shimpei
Author_Institution :
Mitsubishi Electr. Corp., Hyogo, Japan
fDate :
10/1/1988 12:00:00 AM
Abstract :
The authors describe a 14-ns 1-Mb CMOS SRAM (static random-access memory) with both 1M word×1-b and 256 K word×4-b organizations. The desired organization is selected by forcing the state of an external pin. The fast access time is achieved by the use of a shorter divided-word-line (DWL) structure, a highly sensitive sense amplifier, a gate-controlled data-bus driver, and a dual-level precharging technique. The 0.7-μm double-aluminum and triple-polysilicon process technology with trench isolation offers a memory cell size of 41.6 μm2 and a chip size of 86.6 mm 2. The variable bit-organization function reduces the testing time while keeping the measurement accuracy of the access times
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; 0.7 micron; 1 Mbit; 14 ns; Al-Si; CMOS SRAM; divided-word-line; double Al process; dual-level precharging technique; fast access time; gate-controlled data-bus driver; sense amplifier; static RAM; static random-access memory; trench isolation; triple poly-Si process; triple-polysilicon process technology; variable bit organization; Capacitance; Circuit synthesis; Clocks; Decoding; Density estimation robust algorithm; Operational amplifiers; Pulse generation; Random access memory; Read-write memory; Signal detection;
Journal_Title :
Solid-State Circuits, IEEE Journal of
