DocumentCode
12558
Title
An Analytical Yield Model for Zero- 
-Load Thin-Film Transistor Logic Circuits
Author
Jiaqing Zhao ; Qingyu Cui ; Xiaojun Guo
Author_Institution
Dept. of Electron. Eng., Shanghai Jiao Tong Univ., Shanghai, China
Volume
35
Issue
12
fYear
2014
fDate
Dec. 2014
Firstpage
1269
Lastpage
1271
Abstract
This letter presents an analytical circuit yield model for zero-VGS-load thin-film transistor (TFT) logic circuits, which describes the circuit yield as a function of the circuit complexity, threshold voltage dispersion of TFTs, and circuit design parameters. By comparing the calculation result through the model with that by Monte Carlo statistical circuit simulations, the model is proved to be capable of providing a simple and effective way to predict the yield of a given zero-VGS-load TFT circuit design, and is thus applicable for TFT performance evaluation or device and process optimization.
Keywords
Monte Carlo methods; logic circuits; optimisation; thin film transistors; Monte Carlo statistical circuit simulations; TFT logic circuits; analytical circuit yield model; threshold voltage dispersion; zero-VGS-load thin-film transistor logic circuits; Circuit simulation; Complexity theory; Integrated circuit modeling; Inverters; Logic circuits; Monte Carlo methods; Thin film transistors; Monte Carlo simulation; Monte Carlo simulation, noise margin (NM); circuit yield; noise margin $(NM)$; thin-film transistor (TFT); zero- ${V}_{mathrm {GS}}$ -load; zero-V_{GS}load;
fLanguage
English
Journal_Title
Electron Device Letters, IEEE
Publisher
ieee
ISSN
0741-3106
Type
jour
DOI
10.1109/LED.2014.2364860
Filename
6936861
Link To Document