Title :
An 11-ns 8K×18 CMOS static RAM with 0.5-μm devices
Author :
Wong, Donald T. ; Adams, R. Dean ; Bhattacharyya, Arup ; Covino, James ; Gabric, John A. ; Lattimore, George M.
Author_Institution :
IBM Corp., Essex Junction, VT, USA
fDate :
10/1/1988 12:00:00 AM
Abstract :
An experimental 11-ns 8 K×18 static RAM fabricated in a 1.2-μm CMOS technology with 0.5-μm channel lengths is described. Novel interface circuits allow full TTL-level compatibility with a scaled 3.6-V Vdd. Synchronous clocking and automatic restore operations were implemented to realize high-speed access and a fast cycle data rate of 8 ns. Double-word-line architecture and a pulsed word-line technique reduce power dissipation. Other features include on-chip test circuitry that increases tester timing accuracy and word-line redundancy. The design uses a single-poly, double-metal technology with a CMOS six-transistor cell of 235 μm2 to yield a chip size of 60 mm2
Keywords :
CMOS integrated circuits; integrated memory circuits; random-access storage; redundancy; 0.5 micron; 1.2 micron; 11 ns; 144 kbit; 3.6 V; 8 ns; CMOS technology; SRAM; Si; automatic restore operations; channel lengths; double word line architecture; fast cycle data rate; full TTL-level compatibility; high-speed access; interface circuits; memory IC; on-chip test circuitry; power dissipation; pulsed word-line technique; single poly/double metal technology; six-transistor cell; static RAM; synchronous clocking; word-line redundancy; CMOS process; CMOS technology; Circuit testing; Clocks; Driver circuits; MOS devices; Power dissipation; Protection; Random access memory; Timing;
Journal_Title :
Solid-State Circuits, IEEE Journal of
