A 2.5-V, 333-Mb/s/pin, 1-Gbit, double-data-rate synchronous DRAM

Author

Yoon, Hongil ; Cha, Gi-Won ; Yoo, Changsik ; Kim, Nam-Jong ; Kim, Keum-Yong ; Lee, Chang Ho ; Lim, Kyu-Nam ; Lee, Kyuchan ; Jeon, Jun-Young ; Jung, Tae Sung ; Jeong, Hongsik ; Chung, Tae-Young ; Kim, Kinam ; Cho, Soo In

Author_Institution

Memory Product & Technol. Div., Samung Electron. Co. Ltd., Kyungki, South Korea

Volume

34

Issue

11

fYear

1999

fDate

11/1/1999 12:00:00 AM

Firstpage

1589

Lastpage

1599

Abstract

A double data rate (DDR) at 333 Mb/s/pin is achieved for a 2.5-V, 1-Gb synchronous DRAM in a 0.14-μm CMOS process. The large density of integration and severe device fluctuation present challenges in dealing with the on-chip skews, packaging, and processing technology. Circuit techniques and schemes of outer DQ and inner control (ODIC) chip with a non-ODIC package, cycle-time-adaptive wave pipelining, and variable-stage analog delay-locked loop with the three-input phase detector can provide precise skew controls and increased tolerance to processing variations. DDR as a viable high-speed and low-voltage DRAM I/O interface is demonstrated

Keywords

CMOS memory circuits; DRAM chips; delay lock loops; high-speed integrated circuits; integrated circuit packaging; pipeline processing; 0.14 micron; 1 Gbit; 2.5 V; 333 Mbit/s; CMOS process; DDR SDRAM; cycle-time-adaptive wave pipelining; double-data-rate DRAM; dynamic RAM; low-voltage DRAM I/O interface; nonODIC package; onchip skews; packaging; precise skew control; processing variations tolerance; synchronous DRAM; three-input phase detector; variable-stage delay-locked loop; viable high-speed DRAM I/O interface; CMOS process; CMOS technology; Circuits; Detectors; Fluctuations; Packaging; Phase detection; Pipeline processing; Propagation delay; Random access memory;

fLanguage

English

Journal_Title

Solid-State Circuits, IEEE Journal of

Publisher

ieee

ISSN

0018-9200

Type

jour

DOI

10.1109/4.799867

Filename

799867