Title :
A 62-ns 16-Mb CMOS EPROM with voltage stress relaxation technique
Author :
Tomita, Naoto ; Ohtsuka, Nobuaki ; Miyamoto, Jun-ichi ; Imamiya, Ken-ichi ; Iyama, Yumiko ; Mori, Seiichi ; Ohsima, Y. ; Arai, Norihisa ; Kaneko, Yukio ; Sakagami, Eiji ; Yoshikawa, Kuniyoshi ; Tanaka, Sumio
Author_Institution :
Toshiba Corp., Kawasaki, Japan
fDate :
11/1/1991 12:00:00 AM
Abstract :
To meet the increasing demand for higher-density and faster EPROMs, a 16-Mb CMOS EPROM has been developed based on 0.6-μm N-well CMOS technology. In scaled EPROMs, it is important to guarantee device reliability under high-voltage operation during programming. By employing internal programming-voltage reduction and new stress relaxation circuits, it is possible to keep an external programming voltage Vpp of 12.5 V. The device achieves a 62-ns access time with a 12-mA operating current. A sense-line equalization and data-out latching scheme, made possible by address transition detection (ATD), and a bit-line bias circuit with two types of depletion load led to the fast access time with high noise immunity. This 16-Mb EPROM has pin compatibility with a standard 16-Mb mask-programmable ROM (MROM) and is operative in either word-wide or byte-wide READ mode. Cell size and chip size are 2.2 μm×1.75 μm and 7.18 mm×17.39 mm, respectively
Keywords :
CMOS integrated circuits; EPROM; integrated memory circuits; 0.6 micron; 12 mA; 12.5 V; 16 Mbit; 62 ns; CMOS EPROM; N-well CMOS technology; access time; address transition detection; bit-line bias circuit; byte-wide READ mode; data-out latching scheme; device reliability; high noise immunity; high-voltage operation; internal programming-voltage reduction; pin compatibility; sense-line equalization; voltage stress relaxation; word wide READ mode; CMOS process; CMOS technology; Circuit noise; Delay effects; EPROM; Electronic equipment; Helium; Read only memory; Stress; Voltage;
Journal_Title :
Solid-State Circuits, IEEE Journal of
