DocumentCode :
1266161
Title :
Multicycle Tests With Constant Primary Input Vectors for Increased Fault Coverage
Author :
Pomeranz, Irith
Author_Institution :
Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA
Volume :
31
Issue :
9
fYear :
2012
Firstpage :
1428
Lastpage :
1438
Abstract :
Test generation procedures for n -detection test sets improve the quality of a test set by adding tests that increase the numbers of detections of target faults. A different approach to n-detection test generation increases the numbers of detections of target faults within the bounds of the number of tests of a single-detection test set. Multicycle tests provide the flexibility of improving the quality of a test set by increasing the number of clock cycles in each test, without increasing the number of tests. Improved test quality is thus achieved with limited increases in test application time and test data volume due to the larger numbers of clock cycles in each test. This paper describes a procedure that starts from a compact one-detection single-cycle test set for single stuck-at faults and produces a multicycle test set with the same number of tests, but increased numbers of clock cycles and improved test quality. The procedure uses only one-detection fault simulation of single stuck-at faults. A similar procedure is applied starting from a two-cycle test set and considering transition faults. The procedures produce tests with constant primary input vectors to accommodate tester limitations.
Keywords :
automatic test pattern generation; clocks; fault simulation; logic testing; clock cycles; constant primary input vectors; fault coverage; fault detection; multicycle test set; n-detection test generation; n-detection test sets; one-detection fault simulation; one-detection single-cycle test set; single-detection test set; stuck-at faults; test application time; test data volume; test set quality improvement; transition faults; two-cycle test set; Circuit faults; Clocks; Delay; Fault detection; Indexes; Integrated circuit modeling; Vectors; Bridging faults; multicycle tests; scan circuits; single stuck-at faults; transition faults;
fLanguage :
English
Journal_Title :
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
0278-0070
Type :
jour
DOI :
10.1109/TCAD.2012.2193583
Filename :
6269975
Link To Document :
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