Title :
Hierarchical architecture for area-efficient integrated N-port memories with latency-free multi-gigabit per second access bandwidth
Author_Institution :
Res. Center for Nanodevices & Syst., Hiroshima Univ., Japan
fDate :
8/19/1999 12:00:00 AM
Abstract :
A two-level hierarchy is exploited for an area-efficient integrated N-port memory architecture, based on 1-port memory cells. The architecture is applicable to all types of dynamic, static and novolatile memory. It allows simultaneous read/write access from all ports, with access-rejection probability adjustable to application needs
Keywords :
integrated memory circuits; memory architecture; 1-port memory cells; adjustable access-rejection probability; area-efficient integrated N-port memories; dynamic memory; hierarchical architecture; latency-free multi-Gbit/s access bandwidth; memory architecture; multi-gigabit per second access bandwidth; novolatile memory; simultaneous read/write access; static memory; two-level hierarchy;
Journal_Title :
Electronics Letters
DOI :
10.1049/el:19990974
