Title :
Weighing in on logic scaling trends
Author :
Zietzoff, P.M. ; Chung, James E.
fDate :
3/1/2002 12:00:00 AM
Abstract :
In this paper, scaling trends and the associated challenges are discussed from the perspective of the 2001 International Technology Roadmap for Semiconductors (ITRS) for both high-performance and low-power logic technologies. Starting from the overall chip circuit requirements, MOSFET and front-end process integration technology requirements, scaling trends, and challenges are discussed, as well as some of the key potential solutions to the challenges, along with the long-term issues and possible solutions for mobility improvement and optimal scaling for very small transistors. Potential solutions include eventual use of high-k gate dielectrics, metal gate electrodes, and perhaps nonclassical MOSFET devices such as double-gate SOI
Keywords :
integrated circuit technology; integrated logic circuits; low-power electronics; 2001 ITRS; MOSFET integration technology requirements; double-gate SOI; front-end process integration technology; high-k gate dielectrics; high-performance logic technologies; logic scaling trends; low-power logic technologies; metal gate electrodes; nonclassical MOSFET devices; optimal scaling; Acceleration; Circuits; Contact resistance; Dielectrics; Electrodes; Leakage current; Logic design; Logic devices; MOSFETs; Power dissipation;
Journal_Title :
Circuits and Devices Magazine, IEEE