Power-optimal encoding for a DRAM address bus

Author

Cheng, Wei-Chung ; Pedram, Massoud

Author_Institution

Dept. of Electr. Eng. Syst., Univ. of Southern California, Los Angeles, CA, USA

Volume

10

Issue

2

fYear

2002

fDate

4/1/2002 12:00:00 AM

Firstpage

109

Lastpage

118

Abstract

This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed dynamic RAM (DRAM) address bus. The DRAM switching activity can be classified either as external (between two consecutive addresses) or internal (between the row and column addresses of the same address). For external switching activity in a sequential access pattern, we present a power-optimal encoding, named Pyramid code. Extensions of the basic code address different types of DRAM devices. The proposed codes reduce power dissipation on the memory bus by a factor of two or more.

Keywords

DRAM chips; circuit optimisation; circuit simulation; integrated circuit design; low-power electronics; memory architecture; minimisation of switching nets; multiplexing; DRAM address bus; Pyramid code; column addresses; irredundant encoding technique; memory bus; multiplexed dynamic RAM; power dissipation; power-optimal encoding; row addresses; sequential access pattern; switching activity; time-multiplexed bus; Control systems; DRAM chips; Encoding; Energy management; Power dissipation; Power system management; Power system reliability; Quality of service; Random access memory; System-on-a-chip;

fLanguage

English

Journal_Title

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on

Publisher

ieee

ISSN

1063-8210

Type

jour

DOI

10.1109/92.994988

Filename

994988