DocumentCode :
1271064
Title :
Toward better wireload models in the presence of obstacles
Author :
Cheng, Chung-Kuan ; Kahng, Andrew B. ; Liu, Bao ; Stroobandt, Dirk
Author_Institution :
Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA
Volume :
10
Issue :
2
fYear :
2002
fDate :
4/1/2002 12:00:00 AM
Firstpage :
177
Lastpage :
189
Abstract :
Wirelength estimation techniques typically contain a site density function that enumerates all possible path sites for each wirelength in an architecture and an occupation probability function that assigns a probability to each of these paths to be occupied by a wire. In this paper, we apply a generating polynomial technique to derive complete expressions for site density functions which take effects of layout region aspect ratio and the presence of obstacles into account. The effect of an obstacle is separated into two parts: the terminal redistribution effect and the blockage effect. The layout region aspect ratio and the obstacle area are observed to have a much larger effect on the wirelength distribution than the obstacle´s aspect ratio and location. Accordingly, we suggest that these two parameters be included as indices of lookup tables in wireload models. Our results apply to a priori wirelength estimation schemes in chip planning tools to improve parasitic estimation accuracy and timing closure; this is particularly relevant for system-on-chip designs where IP blocks are combined with row-based layout.
Keywords :
application specific integrated circuits; circuit layout CAD; integrated circuit interconnections; integrated circuit layout; table lookup; timing; wiring; IP blocks; blockage effect; chip planning tools; floorplanning; generating polynomial technique; interconnect length estimation; layout region aspect ratio; lookup tables; obstacle area; obstacles; occupation probability function; parasitic estimation accuracy; path sites; row-based layout; site density function; system-on-chip designs; terminal redistribution effect; timing closure; wirelength estimation techniques; wireload models; Accuracy; Delay estimation; Density functional theory; Electronic design automation and methodology; Polynomials; Power system planning; System-on-a-chip; Table lookup; Timing; Wire;
fLanguage :
English
Journal_Title :
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on
Publisher :
ieee
ISSN :
1063-8210
Type :
jour
DOI :
10.1109/92.994997
Filename :
994997
Link To Document :
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