Versatile architecture for block matching motion estimation

A novel architecture for the block matching technique is proposed which can flexibly deal with various sizes of matching block and miscellaneous motion vector prediction modes of the current video coding standards, without extra area and control overhead. The processing element array of the proposed architecture features a separate difference and accumulation unit, considering the balanced delay time among operational data paths and efficient hardware resource utilisation. The VLSI realisation of the proposed architecture using 0.6 μm CMOS technology shows significant improvement over a conventional systolic architecture in both area and speed