Title :
A digital multistandard paging receiver
Author_Institution :
Helsinki Univ. of Technol., Espoo, Finland
fDate :
11/1/1999 12:00:00 AM
Abstract :
Many different paging systems exist. Therefore it is very desirable to be able to implement the paging receiver in a way that all major paging standards can be supported. In this paper, a software radio receiver architecture which uses a signal demodulation technique based on a complex digital phase-locked loop is presented. This kind of software radio receiver can easily handle multiple paging standards, and it can easily be implemented in VLSI using the well-known CORDIC algorithm.
Keywords :
VLSI; demodulation; digital phase locked loops; digital radio; frequency shift keying; paging communication; radio receivers; telecommunication standards; 169 MHz; CORDIC algorithm; VLSI; complex digital phase-locked loop; digital multistandard paging receiver; paging standards; paging systems; software radio receiver architecture; Demodulation; Digital signal processing; Filters; Frequency shift keying; Large Hadron Collider; Radio frequency; Receivers; Signal processing algorithms; Software radio; Very large scale integration;
Journal_Title :
Consumer Electronics, IEEE Transactions on
