Title :
Supply-voltage optimization for below-70-nm technology-node MOSFETs
Author :
Wakabayashi, Hitoshi ; Samudra, Ganesh Shankar ; Djomehri, Ihsan J. ; Nayfeh, Hasan ; Antoniadis, Dimitri A.
Author_Institution :
Microsystems Technol. Labs., MIT, Cambridge, MA, USA
fDate :
5/1/2002 12:00:00 AM
Abstract :
A tradeoff between the performance and power consumption is discussed for below-70-nm technology-node MOSFETs, as a function of power-supply voltage. In order to optimize the supply voltage, gate-delay (CV/I) and energy-delay product (C2V3/I) trends are evaluated using the characteristics of down to 24-nm physical-gate-length nMOSFETs. The gate-delay dependence on the supply voltage down to 0.9 V is almost constant at the same OFF current of 100 nA/μm. On the other hand, an optimum supply voltage for the energy-delay product significantly depends, on the short-channel characteristics, and is interpreted with analytic expressions. Therefore, for the below-70-nm technology node at sub-1.0 V, it is important to design the power-supply voltage taking into consideration of a short-channel effect (SCE)
Keywords :
CMOS integrated circuits; MOSFET; circuit optimisation; delays; integrated circuit design; low-power electronics; nanotechnology; 0.9 V; 24 to 70 nm; CMOS devices; MOSFETs; SCE; below-70-nm technology-node; energy-delay product; gate-delay dependence; gate-delay product; nMOSFETs; power consumption; power-supply voltage; short-channel effect; supply-voltage optimization; CMOS technology; Delay effects; Energy consumption; Laboratories; Large scale integration; MOSFETs; Paper technology; Power dissipation; Power generation; Threshold voltage;
Journal_Title :
Semiconductor Manufacturing, IEEE Transactions on
