DocumentCode
1281045
Title
ARDOR: area optimisation algorithm for cell selection problems
Author
Kim, T.H. ; Kim, Y.H.
Author_Institution
Dept. of Electr. Eng., Pohang Univ. of Sci. & Technol., South Korea
Volume
35
Issue
21
fYear
1999
fDate
10/14/1999 12:00:00 AM
Firstpage
1825
Lastpage
1826
Abstract
The authors present a cell selection algorithm, ARDOR, which optimises the area of the cell-based design under the delay constraint. ARDOR visits a circuit in the forward direction and calculates the lower bound on the delay and area. It then binds the logic gates using the branch-and-bound formulations, while traversing the circuit in the reverse direction. Experimental results show that the ARDOR algorithm optimises the area of test circuits by 27.33% on average
Keywords
circuit layout CAD; circuit optimisation; delay estimation; integrated circuit layout; logic CAD; ARDOR; area optimisation algorithm; branch/bound formulations; cell selection problems; cell-based design; delay constraint; logic gate binding; lower bound;
fLanguage
English
Journal_Title
Electronics Letters
Publisher
iet
ISSN
0013-5194
Type
jour
DOI
10.1049/el:19991238
Filename
809995
Link To Document