A semi 2D analytical Vth model for junctionless double gate nanoscale Silicon on Nothing (JLDG-SON) MOSFET

In this literature, we have derived and proposed a semi 2D analytical model for junctionless (JL) double gate (DG) SON MOSFET by solving 2D Poisson´s equation using variable separation technique. Based on the model derivation, the expressions for central potential, surface potential and threshold voltage (V_th) are developed consequently in this paper. The figures clearly exhibit how the threshold voltage degradation is affected with the variation of the device parameters such as the silicon thickness (t_si), oxide thickness (t_ox), drain bias (V_ds) and channel length (L). Moreover, the variations of V_th roll-off (TVRO), DIBL and subthreshold swing (SS) with the channel length (L) have also come into our consideration.