Performance analysis of a high speed, energy efficient 4×4 dynamic RAM cell array using 32nm fully depleted SOI/SON and CNFET

The objective of this paper is fully focused on designing of a power efficient, high performance 4×4 1T DRAM cell array using conventional MOS, fully depleted SOI/SON and CNFET devices. As the CMOS technology is being scaled down, there has been a major need to improve the performance and robustness of the memory extensively used in today´s hand-held devices. Dynamic Random Access Memory (DRAM) is the main memory used for all desktop and larger computers. In modern VLSI circuit designing, power dissipation is also a crucial issue. The new emerging devices with improved technology promise of low power applications. In this paper, we have presented a comparative circuit level analysis between Metal Oxide Semiconductor (MOS), fully depleted Silicon on Insulator (FD-SOI), fully depleted Silicon on Nothing (FD-SON) and Carbon Nanotube Field Effect transistor (CNFET) in 32nm technology node using HSpice tool.