14-bit two-step successive approximation ADC with calibration circuit for high-resolution CMOS imagers

A 14-bit two-step successive approximation analogue-to-digital converter (SA ADC) for high-resolution CMOS imagers is proposed. The proposed SA ADC consumes a small area because it uses only a capacitor array for 7-bit resolution to implement 14-bit ADC. To enhance accuracy, it uses digital-to-analogue conversion (DAC) embedded reference buffers to calibrate reference voltages. The average switching energy in the capacitor array is only 5.8 pJ per single conversion step. The HSPICE post-layout simulation results show that SNDR of the proposed ADC is improved from 73.41 to 81.52 dB after calibration.