FRISC-E: a 250-MIPS hybrid microprocessor

Author

Grueb, H.J. ; McDonald, J.E. ; Creedon, T.

Author_Institution

Rensselaer Polytech. Inst., Troy, NY, USA

Volume

6

Issue

3

fYear

1990

fDate

5/1/1990 12:00:00 AM

Firstpage

16

Lastpage

25

Abstract

A description is given of the FRISC-E, a 32-bit fast RISC (reduced instruction set computer) design using advanced differential bipolar logic. FRISC-E was designed to solve the problems caused by partitioning high-speed microprocessors, which is necessary to increase yield and reduce heat flux but requires die-to-die interconnections that cause signal propagation delays. The design and packaging of FRISC-E is described, and its use of pipelining is discussed. System architecture and performance are examined.<>

Keywords

bipolar integrated circuits; hybrid integrated circuits; microprocessor chips; packaging; pipeline processing; reduced instruction set computing; 250 MIPS; 32 bit; FRISC-E; RISC; advanced differential bipolar logic; architecture; high-speed microprocessors; packaging; pipelining; reduced instruction set computer; Computer aided instruction; Delay; Distributed parameter circuits; Integrated circuit interconnections; Logic circuits; Logic design; Microprocessors; Pipeline processing; Power transmission lines; Reduced instruction set computing;

fLanguage

English

Journal_Title

Circuits and Devices Magazine, IEEE

Publisher

ieee

ISSN

8755-3996

Type

jour

DOI

10.1109/101.55331

Filename

55331