Real-time digital video stabilization system based on FPGA

An embedded real-time video stabilization system (ERVSS) based on Virtex-5 FPGA of Xilinx is presented. The horizontal and vertical global inter-frame movements of video are estimated by adopting an enhanced integral projection matching approach. The matching range is set to 1/3 view field. The global movements are low-pass filtered to high frequency components caused by platforms vibration and low frequency components representing the intentional motion. The unwanted movements are removed. The stabilization algorithm is mainly programmed in Verilog-HDL language, which is more practical and takes less chip resource. an embedded processor in FPGA executes set-up and control functionality. ERVSS can meet the requirements of real time processing of PAL video. ERVSS works steadily and the time delay is within 40ms.