An investigation of erase-mode dependent hole trapping in flash EEPROM memory cell

Author

Haddad, Sameer ; Chang, Chi ; Wang, Arthur ; Bustillo, J. ; Lien, J. ; Montalvo, T. ; Van Buskirk, M.

Author_Institution

Adv. Micro Devices Inc., Sunnyvale, CA, USA

Volume

11

Issue

11

fYear

1990

Firstpage

514

Lastpage

516

Abstract

Hot-hole generation during electrical erase in flash memory cells was investigated and found to be strongly dependent on the lateral electric field of the gated diode junction. It is shown, by erasing the memory cell at a low source voltage in combination with a negative gate voltage, that the operating point can be chosen well away from the onset of avalanche. Using this erasing scheme appreciably reduces the amount of hole trapping in the tunnel oxide. As a result, data retention is significantly improved as compared with conventional erasure.<>

Keywords

EPROM; MOS integrated circuits; integrated memory circuits; data retention improvement; electrical erase; erase-mode dependent hole trapping; erasing at low source voltage; erasing scheme; erasure modes; flash EEPROM memory cell; flash memory cells; gated diode junction; hole trapping; hot-hole generation; lateral electric field; negative gate voltage; operating point; reduction in tunnel oxide; Current measurement; Dielectric measurements; Diodes; EPROM; Flash memory cells; Hot carriers; Low voltage; Nonvolatile memory; Tunneling; Voltage control;

fLanguage

English

Journal_Title

Electron Device Letters, IEEE

Publisher

ieee

ISSN

0741-3106

Type

jour

DOI

10.1109/55.63017

Filename

63017