An FPGA-based digital class-D amplifier with power supply error correction

This paper presents the design and implementation of a Field Programmable Gate Array (FPGA)-based two-channel digital class-D amplifier with H-bridge power stages. Because in H-bridge power stages the power supply noise can intermodulate with the input signals to cause errors in the outputs, a power supply noise measurement circuit and two correction blocks are employed in the proposed amplifier to correct the errors. An experimental measurement platform with a 55 V linear unregulated power supply was built to measure the proposed amplifier. The results obtained show that the errors caused by the power supply noise can be corrected in the proposed amplifier and the Total Harmonic Distortion + Noise (THD+N) of the proposed amplifier is 0.039% with 1 kHz, -1 dBFS input.